Low power consumption is a key-feature of mobile devices. Mobile devices now provide video encoding and decoding capabilities that are known to dissipate a lot of energy. So-called low-power video algorithms are thus needed.
As a matter of fact, accesses to an external memory such as SDRAM are a bottleneck for video devices. This is due both to power consumption issues, as memories are known to be the most power-consuming part of a system, and to speed limitation because of the bandwidth available for the exchanges between a central processing unit CPU and the memory.
In conventional video decoders, the motion compensation unit needs-many such accesses because it constantly points to blocks of pixels in so-called reference frames. To overcome this problem, so-called “embedded compression” has been proposed. Said embedded compression has originally been developed to decrease the memory size at the expense of a quality decrease, due to lossy compression of the reference frames.
An example of embedded compression is shown in FIG. 1 applied to an H.264 video decoder. Said video decoder comprises in series:
a variable length decoding block VLD suitable for decoding an encoded bit-stream BS so as to produce decoded data blocks on the one hand, and decoded motion vectors MV on the other hand,
an inverse quantizing block IQ suitable for producing quantized data blocks,
an inverse frequency transform block IT, for example in inverse discrete cosine transform block IDCT, for producing inversely transformed data blocks corresponding to a residual error data block e.
The video decoder further includes an adder for adding a motion-compensated data block to a residual error data-block. The motion-compensated data blocks are produced by a modified motion compensation unit MMC comprising in series an embedded encoding unit eENC for producing encoded data blocks, an image memory MEM for storing said encoded data blocks, an embedded decoding unit eDEC and an interpolation filter FIL. The output of the adder is a decoded data block of the output decoded image OF which is then delivered to a display (not represented) and which is also delivered to the embedded encoding unit eENC.
It has been proven in “A Low-Power H.264 Decoder with Graceful Degradation”, by A. Bourge and J. Jung, Proceedings Of Electronic Imaging, VCIP, January 2004, that, given some specific requirements, embedded compression techniques help reducing memory transfers and hence power dissipation. One requirement is that the compression ratio maps the memory structure. This requirement means that a compressed block is stored at convenient access points in the memory. For instance the start address of each encoded data block is word-aligned for a SDRAM memory comprising conventionally words having a predetermined length (e.g. 16, 32 or 64 bits), and the size of the encoded data block is optimized if it fits the size of data requests, i.e. bursts of 1, 2, 4, 6 or 8 words are extracted from the memory during one reading cycle.
A conventional way to respect the above requirement could be to set a fixed compression ratio for each block in order to fit in a data burst. For instance, the reference frame is split into data blocks of 8×8 luminance Y and 4×4 chrominance U and V pixels, said luminance and chrominance components being sampled on 8 bits. Therefore, a data block corresponds to 768 uncompressed bits. If we set a compression factor of 3, one data block gets encoded based on a bit budget allocation of 256 bits, which exactly matches the structure of a memory platform with a 32-bit data bus that accepts 8-word bursts.
However, such a fixed compression ratio method is not optimal in terms of visual quality. Indeed, too few bits might be used to correctly encode complex data blocks resulting in a great loss of information, while some less complex data blocks can be encoded without loss with less than 256 bits resulting in a waste of bits.